Memory device and method of operating the same

ABSTRACT

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

BACKGROUND

In general, memory devices may be volatile memory devices andnon-volatile memory (NVM) devices. Volatile memory devices can storedata while power is provided but may lose the stored data once the poweris shut off. A one-time programmable (OTP) memory device is a type ofNVM often used for read-only memory (ROM). When the OTP memory device isprogrammed, the device cannot be reprogrammed. An eFuse memory cell is atype of OTP memory device that includes a one-transistor, one-resistor(1T1R) configuration. As technology continues to advance and followMoore's law, it is desirable to have devices that have small cell areas.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a schematic block diagram of a memory device, inaccordance with some embodiments.

FIG. 2 illustrates an example configuration of a memory cell, inaccordance with some embodiments.

FIG. 3A illustrates a schematic of an example memory device, inaccordance with some embodiments.

FIG. 3B illustrates the example memory device of FIG. 3A during a readoperation, in accordance with some embodiments.

FIG. 4 illustrates an example memory device, in accordance with someembodiments.

FIG. 5 illustrates an example memory device including a mixed sensingstructures, in accordance with some embodiments.

FIG. 6 illustrates a flowchart of an example method of operating amemory device, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over, or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” “top,” “bottom” and the like, may be used herein forease of description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

As integrated circuit (IC) technology advances, IC features (e.g.,transistor gate length) continue to decrease, thereby allowing for morecircuitry to be implemented in an IC. A memory device may include amatrix of memory cells arranged in rows and columns. A typical memorycell may include a selector transistor and a storage unit such as aresistor (e.g., fuse resistor) or a capacitor. Memory devices also usesense amplifiers to access and detect a stored logic state of theselected memory cell. However, as transistors become smaller, voltagestress issues may arise using current structures. Accordingly, it isbecoming more common to use a stacked transistor structure to, forexample, access the row (e.g., a word line transistor and a cascode gatetransistor) as well as stacked transistors to access the column (e.g.,bit line transistor and a cascode gate transistor), which may reduce avoltage stress on the transistors. However, using stacked transistorscan increase the size of the widths of the transistors in order toprovide the same driving capacity, which causes the overall area of thememory device to increase. Larger memory cells are also undesirablebecause parasitic resistances may increase which may cause additionalpower and compensation.

In this regard, some memory devices are formed with a common word linetransistor (or word line selector) to activate a plurality of columns(via the word line), rather than using a word line transistor for eachmemory cell. A common point between two adjacent memory cells is used asa drain of the word line transistor. This can reduce the amount of areaused by the word line transistors, and because the number of word linetransistors are reduced by a factor of how many memory cells share theword line selector, an effective cell area may be reduced. However,while area is reduced, reliability of the memory device may degrade dueto additional bit line leakage that flow through unselected memorycells. For example, when reading from a memory cell in row 2 and column1 of a memory device, the word line for row 2 is activated (e.g., set toturn-on voltage such as VDD) while the word line for row 1 isdeactivated (e.g., set to turn-off voltage such as 0V). In addition, avoltage of the sense amplifier enable for the selected column may beactivated, thereby allowing current to flow through the bit line of bothmemory cells located in rows 1 and 2 and column 1. A leakage currentpath may form from the bit line to the memory cell on row 1 and column1, which may affect reading from the selected memory cell on row 2 andcolumn 1. An additional leakage current path may be formed from thememory cell row 1 and column 1 to the memory cell row 1 and column 2 dueto a voltage difference in the cascode transistor between the source anddrain. The additional BL leakage can cause read margin and read speeddegradation, leading to worse performance. Accordingly, there is adesire to reduce the leakage current that may occur from unselectedmemory cells.

In the present disclosure, a novel sensing structure and scheme can beused to provide several advantages over the current technology. Forexample, instead of each bit line having its own bit line transistor, acommon bit line transistor may be formed that connect a plurality ofcolumns together. The common bit line transistor may be formed toconnect to a plurality of cascode transistors which are then connectedto the individual bit lines. At a common point that connects the bitline transistor to the plurality of cascode transistors, anothertransistor may be formed that can be connected to ground such thatleakage current may flow to ground. Because the cascode transistorsconnected to the common bit line transistor are all turned on at thesame time, and there is no voltage difference between the source anddrain of the cascode transistor in a selected memory cell (a memory celllocated on row 1 and column 2 in the above example), a leakage currentmay be advantageously reduced and/or canceled and the memory device mayoperate more reliably.

FIG. 1 illustrates a schematic block diagram of a memory device 100, inaccordance with some embodiments. A memory device is a type of an ICdevice. In at least one embodiment, a memory device is an individual ICdevice. In some embodiments, a memory device is included as a part of alarger IC device which comprises circuitry other than the memory devicefor other functionalities.

The memory device 100 comprises at least one memory cell 103 and acontroller (also referred to as “control circuit”) 102 coupled tocontrol an operation of the memory cell 103. In the exampleconfiguration in FIG. 1 , the memory device 100 comprises a plurality ofmemory cells 103 arranged in a plurality of columns and rows in a memoryarray 104. The memory device 100 further comprises a plurality of wordlines WL[0] to WL[m] extending along the rows, a plurality of sourcelines SL[0] to SL[m] extending along the rows, and a plurality of bitlines (also referred to as “data lines”) BL[0] to BL[k] extending alongthe columns of the memory cells 103. Each of the memory cells 103 iscoupled to the controller 102 by at least one of the word lines, atleast one of the source lines, and at least one of the bit lines.Examples of word lines include, but are not limited to, read word linesfor transmitting addresses of the memory cells 103 to be read from,write word lines for transmitting addresses of the memory cells 103 tobe written to, or the like. In at least one embodiment, a set of wordlines is configured to perform as both read word lines and write wordlines. Examples of bit lines include read bit lines for transmittingdata read from the memory cells 103 indicated by corresponding wordlines, write bit lines for transmitting data to be written to the memorycells 103 indicated by corresponding word lines, or the like. In atleast one embodiment, a set of bit lines is configured to perform asboth read bit lines and write bit lines. In one or more embodiments,each memory cell 103 is coupled to a pair of bit lines referred to as abit line and a bit line bar. The word lines are commonly referred toherein as WL, the source lines are commonly referred to herein as SL,and the bit lines are commonly referred to herein as BL. Various numbersof word lines and/or bit lines and/or source lines in the memory device100 are within the scope of various embodiments. In at least oneembodiment, the source lines SL are arranged in the columns, rather thanin the rows as shown in FIG. 1 . In at least one embodiment, the sourcelines SL are omitted.

In the example configuration in FIG. 1 , the controller 102 comprises aword line driver 112, a source line driver 114, a bit line driver 116,and a sense amplifier (SA) 118 which are configured to perform at leastone of a read operation or a write operation. In at least oneembodiment, the controller 102 further includes one or more clockgenerators for providing clock signals for various components of thememory device 100, one or more input/output (I/O) circuits for dataexchange with external devices, and/or one or more controllers forcontrolling various operations in the memory device 100. In at least oneembodiment, the source line driver 114 is omitted.

The word line driver 112 is coupled to the memory array 104 via the wordlines WL. The word line driver 112 is configured to decode a row addressof the memory cell 103 selected to be accessed in a read operation or awrite operation. The word line driver 112 is configured to supply avoltage to the selected word line WL corresponding to the decoded rowaddress, and a different voltage to the other, unselected word lines WL.

The source line driver 114 is coupled to the memory array 104 via thesource lines SL. The source line driver 114 is configured to supply avoltage to the selected source line SL corresponding to the selectedmemory cell 103, and a different voltage to the other, unselected sourcelines SL.

The bit line driver 116 (also referred as “write driver”) is coupled tothe memory array 104 via the bit lines BL. The bit line driver 116 isconfigured to decode a column address of the memory cell 103 selected tobe accessed in a read operation or a write operation. The bit linedriver 116 is configured to supply a voltage to the selected bit line BLcorresponding to the decoded column address, and a different voltage tothe other, unselected bit lines BL. In a write operation, the bit linedriver 116 is configured to supply a write voltage (also referred to as“program voltage”) to the selected bit line BL. In a read operation, thebit line driver 116 is configured to supply a read voltage to theselected bit line BL.

The SA 118 is coupled to the memory array 104 via the bit lines BL. In aread operation, the SA 118 is configured to sense data read from theaccessed memory cell 103 and retrieved through the corresponding bitlines BL. The described memory device configuration is an example, andother memory device configurations are within the scopes of variousembodiments. In at least one embodiment, the memory device 100 is NVM,and the memory cells 103 are OTP memory cells. Other types of memory arewithin the scopes of various embodiments. Example memory types of thememory device 100 include, but are not limited to, eFuse, anti-fuse,magnetoresistive random-access memory (MRAM), or the like.

The transistors in this disclosure are shown to have a certain type(n-type or p-type), but embodiments are not limited thereto. Thetransistors can be any suitable type of transistor including, but notlimited to, metal oxide semiconductor field effect transistors (MOSFET),complementary metal oxide semiconductors (CMOS) transistors, P-channelmetal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors(NMOS), bipolar junction transistors (BJT), high voltage transistors,high frequency transistors, P-channel and/or N-channel field effecttransistors (PFETs/NFETs), FinFETs, planar MOS transistors with raisedsource/drains, nanosheet FETs, nanowire FETs, or the like. Furthermore,although each of the access transistors T0-T7 are shown in FIG. 1B asone transistor, embodiments are not limited thereto. For example, eachof the access transistors T0-T7 can include more than one transistor(“sub-transistor”) that are connected to one another in parallel. Forexample, each of the sub-transistors of access transistor T0 can includea gate that is connected to the word line WL0, a source terminal that isconnected to ground, and drain terminal that is connected to the fuseresistor R0.

In some embodiments, the controller 102 includes the word line driver112, source line driver 114, bit line driver 116, and sense amplifier118, as well as a plurality of other circuits such as one or moremultiplexors, one or more pass gate transistors (or pass transistors),and/or one or more level shifters, where each of these other circuitscan include p-type or n-type transistors. The multiplexors, the passgate transistors, the sense amplifier 118, and the level shifters can begenerally disposed on opposing sides of the word line driver 112, sourceline driver 114, and/or bit line driver 118. The controller 102 can bedisposed on the substrate and connected to the memory array 104 throughone or more bit lines BL, one or more source lines SL and/or one or moreword lines WL that can be disposed in one or more metallization layersand/or one or more via structures.

FIG. 2 illustrates an example configuration of the memory cell 103 (FIG.1 ), in accordance with some embodiments. In FIG. 2 , the memory cell103 includes an eFuse cell that is implemented as a 2T1R configuration,for example, a fuse resistor 202 serially connected to a stackedtransistors including a cascode gate (CG) (or control gate) transistor204 a and an access transistor 204 b. The CG transistor 204 a may beprovided to reduce a voltage stress on both the access transistor 204 b.It, however, should be understood that any of various other fuseconfigurations that exhibit the fuse characteristic may be used by thememory cell 103 such as, for example, 1T1R, a 2-diodes-1-resistor (2D1R)configuration, a many-transistors-one-resistor (manyT1R) configuration,etc., while remaining within the scope of the present disclosure.Furthermore, the described technology is not limited to eFuse memorydevices but can be applied to any memory that uses a transistor as aselector and a storage element such as a resistor or a capacitor.

In accordance with various embodiments of the present disclosure, thefuse resistor 202 is formed of one or more metal structures. Forexample, the fuse resistor 202 may be one of a number of interconnectstructures in one of a number metallization layers that are disposedabove or below the CG transistor 204 a and/or the access transistor 204b. Specifically, both of the CG transistor 204 a and the accesstransistor 204 b are formed over a major surface of a semiconductorsubstrate, which is sometimes referred to as part of front-end-of-line(FEOL) processing. Over the FEOL processing, a number of metallizationlayers, each of which includes a number of interconnect (e.g., metal)structures, are typically formed, which are sometimes referred to aspart of BEOL processing. During the BEOL processing, or between the FEOLand BEOL processing, there can be processing steps where localelectrical connections between transistors and metal gate contacts areformed during the MEOL processing.

With the fuse resistor 202 (of the memory cell 103) embodied as a metalstructure, the fuse resistor 202 may present an initial resistance value(or resistivity), for example, as fabricated. To program the memory cell103, both of the CG transistor 204 a and the access transistor 204 b (ifembodied as an n-type transistor) are turned on by applying a (e.g.,voltage) signal, corresponding to a logic high state, through a CG line(CGL) or a WL to a gate terminal of the access transistor 204 b.Concurrently or subsequently, a high enough (e.g., voltage) signal isapplied on one of the terminals of the fuse resistor 202 through a BL.With the CG transistor 204 a and the access transistor 204 b turned onto provide a (e.g., program) path from the BL, through the fuse resistor202, CG transistor 204 a, and access transistor 204 b, and to a SL, sucha high voltage signal can burn out a portion of the corresponding metalstructure (the fuse resistor 202), thereby transitioning the fuseresistor 202 from a first state (e.g., a short circuit) to a secondstate (e.g., an open circuit). Accordingly, the memory cell 103 canirreversibly transition from a first logic state (e.g., logic 1) to asecond logic state (e.g., logic 0), which can be read out by applying arelatively low voltage signal on the BL and turning on the CG transistor204 a and the access transistor 204 b to provide a (e.g., read) path.

FIG. 3A illustrates a schematic of an example memory device 300, inaccordance with some embodiments. The memory device 300 includes CGtransistors 322, 324 . . . 322 n, 324 n, 342, 344 . . . 342 n, 344 n(e.g., CG transistor 204 a of FIG. 2 ), shared gate (SG) transistors302, 304 . . . 302 n, 304 n, a sense amplifier 310 (e.g., senseamplifier 118 of FIG. 1 ), control transistors 312 . . . 312 n, andsense enable transistors (or mux transistor) 382 . . . 382 n. The memorydevice 300 also may include a plurality of rows of memory cells.Furthermore, a plurality of signal lines carrying control signals areprovided to the memory device 300, such as word line WL0, WL1, bit linesBL0, BL1 BLn, and BLm, and cascode gate (CG) lines CG0, CG1 . . . CGn,CGm. Although only a certain number of signal lines are shown, one ofordinary skill will recognize that there may be more or fewer signallines. Further, although the memory device 300 is shown to have acertain circuit in FIG. 3A, embodiments are not limited thereto, and thedescribed technology can be applied to any memory circuit that usessense amplifiers. For example, as disclosed above, the memory cells caninclude eFuse, anti-fuse, metal-insulator-metal (MIM) memories, otherone-time programmable (OTP) memories, dynamic random access memory(DRAM), and any other memory that uses a resistor or a capacitor as astorage unit.

Fuses 362, 364 . . . 362 n, 364 n, CG transistors 322, 324 . . . 322 n,324 n, and WL transistors 332 . . . 332 n (e.g., WL transistor 204 b ofFIG. 2 ) may form a plurality of memory cells along bit line BL0 and bitline BL1. Fuse 362, CG transistor 322, and WL transistor 332 may form afirst memory cell M1. Fuse 364, CG transistor 324, and WL transistor 332may form a second memory cell M2. Fuse 372, CG transistor 342, and WLtransistor 352 may form a third memory cell M3. Fuse 374, CG transistor344, and WL transistor 352 may form a fourth memory cell M4. Fuses 372,374 . . . 372 n, 374 n, CG transistors 342, 344 . . . 342 n, 344 n, andword line transistors 352 . . . 352 n may form a plurality of memorycells along bit line BLn and bit line BLm. Fuse 362 n, CG transistor 322n, and WL transistor 332 n may form a fifth memory cell M5. Fuse 364 n,CG transistor 324 n, and WL transistor 332 n may form a sixth memorycell M6. Fuse 372 n, CG transistor 342 n, and WL transistor 352 n mayform a seventh memory cell M7. Fuse 374 n, CG transistor 344 n, and WLtransistor 352 n may form an eighth memory cell M8. As discussed above,although this disclosure discusses memory cells with respect to a 2T1Rconfiguration of a fuse (e.g., eFuse) memory cell, embodiments are notlimited thereto, and the disclosed technology may be applied to anymemory device including a sense amplifier to detect stored logic statesin the memory cells.

The mux transistors 382 to 382 n may be controlled by a mux controlsignal provided on mux control lines 392 to 392 n. Although a not shown,a controller (e.g., controller 102 of FIG. 1 ) may include a decoderthat may be used to provide the control signal to the mux control lines392 to 392 n. Each of the SG transistors 302-302 n and 304-304 n may becontrolled by the same gate control signal provided on control line 390.Further, the controller may include a decoder that may provide thecontrol signal to the control line 390.

Each of the first to eighth memory cells M1 to M8 may operate similar tothe memory cell 103. In some embodiments, the selector for theparticular cell may include the CG transistor (e.g., CG transistor 204a) stacked with the WL transistor (e.g., WL transistor 204 b) to dividethe voltage of an end of the fuse 362. This may help reduce a voltagestress on the CG and WL transistors for half-selected cases (e.g.,either row or column is selected). For example, for the first memorycell, in order to program the fuse 362, a control signal (e.g., logichigh) may be provided to the CG transistor 322 so that the user mayeither program (or write to) or read from the fuse 362 when the WL0 isturned on.

FIG. 3B illustrates the example memory device 300 of FIG. 3A during aread operation, in accordance with some embodiments. Although FIG. 3A isdescribed in reference to reading from the memory cell including fromfuse 372, embodiments are not limited thereto, the present technologymay be applied when reading from any other memory cell within memorydevice 300. Further, reference numerals for certain signal lines in FIG.3B are shown with the logical signal that is provided to those signallines in parentheses for convenience.

When reading from memory cell M3, several signal lines may be activated(e.g., provided with a logic high signal). For example, after the bitline BL0 has been pre-charged to a predetermined level, the mux controlline 392 may receive a logic high signal so that the memory cellsconnected to the two columns on BL0 and BL1 may be sensed. The muxcontrol line 390 and the control line 392 may receive a logic highsignal. The control line 394 may receive a logic low signal. The wordline WL1 may receive a logic high signal. Accordingly, a current pathIcell may be formed from the bit line BL0 to the ground. If the fuse 372in memory cell M3 has not been burned off (e.g., short circuit), thecharge from the bit line BL0 will flow to the ground through the fuse372, the CG transistor 342, and the WL transistor 352. When the senseamplifier 310 senses the bit line BL0, the sense amplifier 310 willsense or detect that there is no charge on bit line BL0, and provide alogic low signal back to the controller, indicating that the memory cellM3 has a logic 0. If the memory cell M3 has a fuse 372 that has beenburned (e.g., open circuit), the charge on the bit line BL0 will remainand the sense amplifier 310 can detect that the memory cell M3 has alogic 1.

During the read operation of the memory cell M3 having a logic 1, memorycell M1 may be half-selected because the control signal may be activatedon CG line CGO but the word line WL0 is not activated. However, there isno leakage current path that is formed in M2 because both the source anddrain of the CG transistor 324 is high, and there is no voltagedifference for a current to be formed. For example, a node N1 connectingthe CG transistor 322, CG transistor 324, and the WL transistor 332 hasa high voltage level, and a node N2 connecting the fuse 364 and the CGtransistor 324 also has a high voltage level. And because the CGtransistor 324 has a gate terminal that is set to logic 0 and a voltagedifference between source and drain terminals is substantially 0V, thereis no leakage current across the CG transistor 324. Therefore, a leakagecurrent is reduced.

Accordingly, the BL leakage caused in the memory cell M2 can be reducedand/or eliminated. In some embodiments, both the read margin and theread speed can be improved. Furthermore, the memory cell area can bereduced by using a common transistor or a set of common transistors toselect all of the columns connected to the same mux transistor, withoutsuffering from read margin degradation.

FIG. 4 illustrates an example memory device 400, in accordance with someembodiments. The memory device 400 is similar to the memory device 300of FIG. 3 except that there are four columns (e.g., corresponding to bitlines BL0, BL1, BL2, and BL3) connected to one word line transistor 432,SG transistor(s) 402, 404, 406, and 408, and control transistor 412.Similar descriptions are omitted for the sake of simplicity and clarity.

For example, memory device 400 has a plurality of memory cells M5, M6,M7, M8, M9, M10, M11, and M12, where memory cells M5-M8 are connected toone WL transistor 432 which is gated by word line WL0, and memory cellsM9-M12 are connected to one WL transistor 452 which is gated by wordline WL1. Furthermore, bit lines BL0-BL3 are respectively connected toSG transistors 402-408 which have gate terminals that are connectedtogether such that the SG transistors 402-408 all have a shared gateterminal. The shared gate terminal can receive a control signal that canactivate all of the SG transistors 402-408.

During a read operation of the memory cell M9, the word line WL1 isactivated and word line WL0 is not activated. There may be a leakagecurrent from the bit line BL3 to the memory cell M6 that may be reducedor avoided because a voltage difference between node N3 and node N4 issubstantially 0V.

Although memory device 400 shows each WL transistor being connected tofour memory cells (e.g., WL transistor 432 is connected to memory cellsM5-M8, WL transistor 452 is connected to memory cells M9-M12),embodiments are not limited thereto, and there can be moreconfigurations of the memory device 400. For example, in anotherconfiguration, each WL transistor may be connected to M number of memorycells per group, and N number of groups of M memory cells per group,totaling M×N number of memory cells per row, where each of M and N is apositive integer. For example, in a row with 32 memory cells configuredto be sensed by a sense amplifier, there may be 8 groups of memory cellswith 4 memory cells per group. Accordingly, a plurality ofconfigurations of M and N may be contemplated.

FIG. 5 illustrates an example memory device 500 including a mixedsensing structures, in accordance with some embodiments. The examplememory device 500 includes a first sensing structure 500 a and a secondsensing structure 500 b. The first sensing structure 500 a includes asensing structure similar to the same sensing structure described withrespect to FIGS. 3A-4 . For example, the sensing structure 500 a mayinclude SG transistors 502 (e.g., SG transistor 302, 402), SG transistor504 (e.g. SG transistor 504), control transistor 512 (e.g., controltransistor 312), and mux transistor 582 (e.g., mux transistor 382).Furthermore, the SG transistors 502 and 504 may be gated by control line590 (e.g., control line 390), control transistor 512 may be gated bycontrol line 594 (e.g., control line 394), and the mux transistor 582may be gated by the mux control line 592 (e.g., mux control line 392).Therefore, similar descriptions are omitted.

The second sensing structure 500 b may include a typical sensingstructure and structure where each bit line BLn and BLm is connected totwo stacked transistors in series for column access to sense the memorycells connected to the bit lines BLn and BLm. For example, the bit lineBLn can be connected to the first stacked transistor 522 n and secondstacked transistor 524 n such that when both transistors are turned onvia control lines 592 n and CGn having active high signals, a voltage onthe bit line BLn can be sensed by the sense amplifier 510. Another setof stacked transistors 532 n and 534 n may be provided to ground so thata leakage current can flow to ground when control signals 544 and CGnare active high. The bit line BLm can be connected to the third stackedtransistor 522 m and fourth stacked transistor 524 m such that when bothtransistors are turned on via control lines 592 m and CGm having activehigh signals, a voltage on the bit line BLm can be sensed by the senseamplifier 510. Another set of stacked transistors 532 m and 534 m may beprovided to ground so that a leakage current can flow to ground whencontrol signals 546 and CGm are active high.

Accordingly, a memory device 500 having mixed sensing structures may beprovided depending on embodiments and design requirements. In someembodiments, the sensing structures 500 a and 500 b may be usedalternatingly for each group of memory devices. In some otherembodiments, the sensing structure 500 a may be used in a first X numberof columns, and the sensing structure 500 b may be used in a Y number ofcolumns following the X number of columns, where X and Y are positiveintegers. Further, any combination of sensing structures 500 a and 500 bmay be used.

FIG. 6 illustrates a flowchart of an example method 600 of operating amemory device, in accordance with some embodiments. The method 600 maybe used to read from a memory cell with a wide read margin. For example,at least some of the operations described in the method 600 operate thememory devices 100, 300, 400 or 500. It is noted that the method 600 ismerely an example and is not intended to limit the present disclosure.Accordingly, it is understood that additional operations may be providedbefore, during, and after the method 600 of FIG. 6 , and that some otheroperations may only be briefly described herein.

In brief overview, the method 600 starts with operation 602 ofactivating, during a read operation of a first memory cell, a first wordline connected to the first memory cell and a second memory cell. Themethod 600 proceeds to operation 604 of activating a first control gateline connected to the first memory cell. The method 600 proceeds tooperation 606 of activating a mux control line connected to a muxtransistor, the mux transistor connected to a sense amplifier. Themethod 600 proceeds to operation 608 of activating a common gate signalline connected to a gate terminal of a first connected to the firstmemory cell and a gate terminal of the second common gate transistorconnected to the second memory cell.

Referring to operation 602, during a read operation of a first memorycell (e.g., memory cell M3 of FIG. 3B), a first word line (e.g., wordline WL1) that is connected to both the first memory cell and a secondmemory cell (e.g., memory cell M4) is activated by a controller (e.g.,controller 102). A word line transistor (e.g., WL transistor 352) may beshared by the first and second memory cells.

Referring to operation 604, a first control gate line (e.g., cascodegate line CGO) may be activated. The first control gate line may extendin the same direction as the bit lines.

Referring to operation 606, a mux control line (e.g., mux control line392) connected to a mux transistor (e.g., mux transistor 382) may beactivated. The mux transistor may be connected to a sense amplifier(e.g., sense amplifier 310). The mux control line may control whether ornot the sense amplifier may sense a current from the first memory cellduring the read operation.

Referring to operation 608, a common gate signal line (e.g., controlline 390) may be activated. The common gate signal may be connected to agate terminal of a first common gate transistor (e.g., shared gatetransistor 302) connected to the first memory cell and a gate terminalof the second common gate transistor connected to the second memorycell.

Accordingly, a leakage current from an unselected memory cell may bereduced and/or eliminated during a read operation of a selected memorycell. Further, a sensing structure connected to the memory cells mayhave a reduced area while still having good read margins, therebyoptimizing the area without sacrificing reliability and performance. Thedisclosed technology may be applied to various memory configurationswith various sensing structures such that one word line may activate aplurality of memory cells on the same row.

In one aspect of the present disclosure, a memory device is disclosed.The memory device includes a plurality of memory cells including a firstmemory cell and a second memory cell, a first bit line connected to thefirst memory cell, a second bit line connected to the second memorycell, a first word line connected to the first and second memory cells,a first control transistor connected to the first bit line, a secondcontrol transistor connected to second bit line, a first mux transistorcommonly connected to the first and second control transistors, and asense amplifier connected to the first mux transistor.

In another aspect of the present disclosure, a method of operating amemory device is disclosed. The method includes activating, during aread operation of a first memory cell, a first word line connected tothe first memory cell and a second memory cell, activating a firstcontrol gate line connected to the first memory cell, activating a muxcontrol line connected to a mux transistor, the mux transistor connectedto a sense amplifier, and activating a common gate signal line connectedto a gate terminal of a first common gate transistor connected to thefirst memory cell and a gate terminal of the second common gatetransistor connected to the second memory cell.

In yet another aspect of the present disclosure, a memory system isdisclosed. The memory system includes a plurality of memory cellsincluding a first memory cell and a second memory cell, a senseamplifier connected to the plurality of memory cells via a plurality ofbit lines, and a controller connected to the plurality of memory cells.The controller is configured to activate, during a read operation of afirst memory cell, a first word line connected to the first memory celland a second memory cell, activate a first control gate line connectedto the first memory cell; activate a mux control line connected to a muxtransistor, the mux transistor connected to a sense amplifier, andactivate a common gate signal line connected to a gate terminal of afirst common gate transistor connected to the first memory cell and agate terminal of the second common gate transistor connected to thesecond memory cell.

As used herein, the terms “about” and “approximately” generally meanplus or minus 10% of the stated value. For example, about 0.5 wouldinclude 0.45 and 0.55, about 10 would include 9 to 11, about 1000 wouldinclude 900 to 1100.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A memory device, comprising: a plurality ofmemory cells including a first memory cell and a second memory cell; afirst bit line connected to the first memory cell; a second bit lineconnected to the second memory cell; a first word line connected to thefirst and second memory cells; a first control transistor connected tothe first bit line; a second control transistor connected to second bitline; a first mux transistor commonly connected to the first and secondcontrol transistors; and a sense amplifier connected to the first muxtransistor.
 2. The memory device of claim 1, wherein the first andsecond control transistors each has a gate terminal connected to acommon gate control line.
 3. The memory device of claim 2, furthercomprising a controller, during a read operation of the first memorycell connected to the first word line, configured to: activate the firstword line; activate a common gate control line; and activate a muxcontrol line connected to a gate terminal of the first mux transistor.4. The memory device of claim 3, further comprising a third controltransistor connected to the first and second control transistors andground.
 5. The memory device of claim 4, wherein the controller, duringthe read operation, is further configured to deactivate a control lineconnected to a gate terminal of the third control transistor.
 6. Thememory device of claim 5, further comprising a second word lineconnected to third and fourth memory cells of the plurality of memorycells.
 7. The memory device of claim 6, wherein the controller isconfigured to, during the read operation, deactivate the second wordline.
 8. The memory device of claim 1, wherein the plurality of memorycells each comprise a storage unit including a resistor or a capacitor.9. The memory device of claim 1, wherein the first word line isconnected to an M number of the plurality of memory cells, and the senseamplifier is connected to an N number of mux transistors including thefirst mux transistor, where M and N are positive integers.
 10. Thememory device of claim 9, wherein a number of a plurality of controltransistors, including the first and second control transistors,connected to a common gate line and a plurality of bit lines, includingthe first and second bit lines, connected to the mux transistor areequal to M.
 11. A method of operating a memory device, comprising:activating, during a read operation of a first memory cell, a first wordline connected to the first memory cell and a second memory cell;activating a first control gate line connected to the first memory cell;activating a mux control line connected to a mux transistor, the muxtransistor connected to a sense amplifier; and activating a common gatesignal line connected to a gate terminal of a first common gatetransistor connected to the first memory cell and a gate terminal of thesecond common gate transistor connected to the second memory cell. 12.The method of claim 11, further comprising deactivating a second wordline having a drain terminal connected to the first control gatetransistor and a second control gate transistor and a source terminalconnected to the ground.
 13. The method of claim 11, further comprisingdeactivating a second control gate line connected to the second memorycell.
 14. The method of claim 11, wherein the memory cell includes astorage unit including a resistor or a capacitor.
 15. The method ofclaim 11, wherein the first and second common gate transistors, the muxtransistor, and the control transistor are connected to one another at anode.
 16. A memory system, comprising: a plurality of memory cellsincluding a first memory cell and a second memory cell; a senseamplifier connected to the plurality of memory cells via a plurality ofbit lines; and a controller connected to the plurality of memory cells,wherein the controller is configured to: activate, during a readoperation of a first memory cell, a first word line connected to thefirst memory cell and a second memory cell; activate a first controlgate line connected to the first memory cell; activate a mux controlline connected to a mux transistor, the mux transistor connected to asense amplifier; and activate a common gate signal line connected to agate terminal of a first common gate transistor connected to the firstmemory cell and a gate terminal of the second common gate transistorconnected to the second memory cell.
 17. The memory system of claim 16,wherein the controller is further configured to deactivate a second wordline having a drain terminal connected to the first control gatetransistor and a second control gate transistor and a source terminalconnected to the ground.
 18. The memory system of claim 16, wherein thecontroller is further configured to deactivate a second control gateline connected to the second memory cell.
 19. The memory system of claim16, wherein the plurality of memory cells each include a storage unitincluding a resistor or a capacitor.
 20. The memory system of claim 16,wherein the first and second common gate transistors, the muxtransistor, and the control transistor are connected to one another at anode.